Dark Silicon
Ivan Sutherland played a key role in foundational computer technologies back in the 1970s. He won most if not all the major awards—the Turing Award and the Kyoto Prize in particular.
Now he sees a path for America to claim the mantle in “micro” chips. Check out this recent New York Times article on his view.
Dark Silicon
His insights are based on what is called Dark Silicon. If all the billions of transistors on a modern microprocessor chip are used simultaneously, the heat they create will melt the chip. This is bad—to use a technical term. Thus entire sections of modern chips are shut down and only some of the transistors are working at any time. This reins in energy use but makes the chips far less efficient overall.
The upshot is that parts of a modern chip must be dark.
A Challenge
As math-oriented types we find this issue quite interesting. See this paper for more on the practical issues and this too. But the question could we feel be viewed as a theory type question.
Just as we in complexity theory study time and space of computations, can we study them from the view of dark silicon?
Is there some formal model that forces computations to use dark silicon in some clever way? Just like computations that save space or even time could there be power-smart computations? Ken’s Buffalo colleague Atri Rudra, his student Swapnoneel Roy (now tenured at the University of North Florida), and Akshat Verma of IBM India created an energy consumption model that addresses various components. Can we solve some problem with a dark silicon algorithm? Is it possible to do this with some clever methods?
This seems like a possible formal theory problem. It also seems possible that certain encodings could be possible to reduce the cost of computation. Perhaps by encoding the problem in a clever way we could make the dark part of the computation smaller?
Open Problems
Is there some hope to study computations from the dark silicon direction? Is this a possible formal question?
Another possibility is to minimize “energy complexity”, which informally is defined to be the maximum (over all inputs) number of gates in the circuit which output 1, as in
https://igi-web.tugraz.at/PDF/163.pdf
This is a simple measure but I’m not sure to what extent it corresponds to “dark silicon”. If the overall number of 1s is significantly smaller than the number of 0s, then the entire computation trace is always highly compressible…
This has brought this paper to my memory:
J. Smith, “Space-Time Algebra: A Model for Neocortical Computation,” 2018 ACM/IEEE 45th Annual International Symposium on Computer Architecture (ISCA), Los Angeles, CA, USA, 2018, pp. 289-300, doi: 10.1109/ISCA.2018.00033.
He proposes to use a time-based encoding such as the supposedly employed by neurons. With this, part of the computation cost is delegated to the passage of time, which can be considered “free” in some sense.
The assumption in the first paper (on c-cores) is a fixed 80W power budget. In real life, if you need more processing, you buy a bigger cooler. Processing per Watt is something that’s interesting, but they seem to be trying to get around simple reality with hand waving. (They’re working with a 45nm process, which is like ancient history, so the paper’s odd in a variety of ways. Odd isn’t a nice word: they’re playing in the dedicated hardware part of the industry, which is a different game from the assumption of a computer being a general-purpose device. But a quick glance has me thinking that they’re trying too hard.)
Which is to say, I’m not impressed by the dark silicon idea. It’s thermal resistance per unit area that’s the question, and for current high-end CPUs on desktops, water coolers seem to be working fine. (The peecee this is being typed on is my second water-cooled peecee; water cooling CPUs is old news.)
(Guy Steele had some water powered (not cooled) computer jokes in his Foonley comics from back in the 1970s or so. “That disk drive looks like a washing machine because it is a washing machine”, bit buckets that caught leaks from piping and similar sorts of things. HIghly recommended if you can find them.)
Another thing I’m thinking is that since chips are friggin’ enormous nowadays, local heating that would melt the chip if every CPU were running that hard, would melt the chip locally if even one were running that hard. That is, it’s thermal resistance per unit area (from chip to cooler) that’s the parameter of question. (Plus, of course, the total heat dissipation capacity of the cooler sitting on the CPU’s package. But, like I said, if you need more computrons, you buy a bigger cooler.)
FWIW, from memory (of an article I read a couple of days ago), Intel is moving from four chiplets to two in their next gen server CPU (from something like 15 cores per chiplet to 33, with bad cores (one or two?) allowed for a 64-core instead of 60 core server CPU (and enormously more cache). Since (a) Intel needs to cough up more computation at each generation and (b) they are reducing the number, and increasing the size of the chips, they’re assuming users will have no problem providing cooling adequate to remove the heat generated at full-tilt operation.
Note that this is exactly the opposite direction you’d go if local heating in larger chips was a problem…